Critical Role of Polymer Gate Dielectrics on the Charge Carrier Transport in Perovskite Field-Effect Transistors

Charge transport in 2D tin perovskite FETs is shown to be governed by dielectric interface behavior. Polar polymer dielectrics induce dipolar disorder that localizes carriers, whereas nonpolar polymer suppress trapping and enable superior charge transport, ensuring stable and reliable transistor operation.

In this work, we address the role of the perovskite/dielectric interface by systematically investigating polymer gate dielectrics with different dielectric constants as interlayers on inorganic SiO₂ in perovskite field-effect transistors, more specifically we used phenethylammonium tin iodide ((PEA)₂SnI₄) as a model semiconductor. Our results reveal that high-k polymer dielectrics induce strong dipolar disorder at the interface, which localizes charge carriers and lowers in this way their transport resulting in unreliable device behavior. In contrast, low-k polymers reduce the interfacial charge localization and effectively passivate hydroxyl trapping groups on SiO₂, leading to stable perovskite transistor operation. These findings not only elucidate the chemical origins of interfacial charge trapping and localization but also provide clear guidelines for designing dielectric interfaces to optimize both electronic performance and operational stability of perovskite transistors.​